Weihua Xiao [CV] 肖伟华

       Fifth-year PhD Student at Emerging Computing Technology Laboratory (ECTL)
       University of Michigan–Shanghai Jiao Tong University Joint Institute (UM-JI), Shanghai
       Email: 019370910014@sjtu.edu.cn
       [Github] [Google scholar]

[Biography] [Publications] [Professional Activities] [Major Awards]

Biography [back top]

I am currently a fifth-year PhD student at the Emerging Computing Technology Laboratory (ECTL) of SJTU. I am fortunate to work with Prof. Weikang Qian. Additionally, I was a visiting PhD student at University of Alberta under supervision of Prof. Jie Han from 2023/01 to 2024/01. I will receive my Ph.D. degree in June from Shanghai Jiao Tong University. I study electronic design automation (EDA). My research interests lie in logic synthesis and analysis for emerging computing paradigms, such as approximate computing, stochastic computing. I am also interested at solving combinatorial optimization problems in EDA based on advanced algorithms, such as SAT/SMT, Mixed Integer Programming (MIP), Ising Model, Reinforcement Learning (RL), and Evolutionary Algorithms.

Publications [back top]

Conference Papers

C007. Weihua Xiao$, Tingting Zhang$, Xingyue Qian, Jie Han and Weikang Qian^✉ ($equal contribution)
Efficient Approximate Decomposition Solver using Ising Model [pdf] [code]
To appear in Design Automation Conference (DAC), San Francisco, CA, USA, 2024.
Acceptance Rate: 23%.

C006. Weihua Xiao, Shanshan Han, Yue Yang, Shaoze Yang, Cheng Zheng, Jingsong Chen, Tingyuan Liang, Lei Li, and Weikang Qian^✉
MiniTNtk: An Exact Synthesis-based Method for Minimizing Transistor Network [pdf] [code]
International Conference on Computer-Aided Design (ICCAD), San Francisco, CA, USA, 2023.
Acceptance Rate: 23%.

C005. Weihua Xiao, and Weikang Qian^✉
ASPPLN: Accelerated Symbolic Probability Propagation in Logic Network [pdf] [code]
International Conference on Computer-Aided Design (ICCAD), San Francisco, CA, USA, 2022.
Acceptance Rate: 22.5%.

C004. Weihua Xiao, Cheng Zhuo, and Weikang Qian^✉
OPACT: Optimization of Approximate Compressor Tree for Approximate Multiplier [pdf] [code]
Design, Automation & Test in Europe Conference & Exhibition (DATE), Antwerp, Belgium, 2022.
Acceptance Rate: 25%.

C003. Weihua Xiao, Weikang Qian^✉, and Weiqiang Liu
GOMIL: Global Optimization of Multiplier by Integer Linear Programming [pdf] [code]
Design, Automation & Test in Europe Conference & Exhibition (DATE), Antwerp, Belgium, 2021.
Acceptance Rate: 23.9%.

C002. Chenfei Lou, Weihua Xiao, Weikang Qian^✉
Quantified Satisfiability-based Simultaneous Selection of Multiple Local Approximate Changes under Maximum Error Bound [pdf]
International Symposium on Circuits and Systems (ISCAS), Austin, Texas, USA, 2022.

C001. Chen Wang, Weihua Xiao, Weikang Qian
Exploring Target Function Approximation for Stochastic Circuit Minimization [pdf]
International Conference on Computer-Aided Design (ICCAD), virtual event, 2020.
Acceptance Rate: 27.0%.

Journal Papers

J001. Yi Wu, Chuangtao Chen, Weihua Xiao, Xuan Wang, Chenyi Wen, Jie Han, Xunzhao Yin, Weikang Qian, and Chuo Zhuo^✉
A Survey on Approximate Multiplier Designs for Energy Efficiency: From Algorithms to Circuits [pdf] [code]
ACM Transactions on Design Automation of Electronic Systems (TODAES), 2023.

Projects [back top]

ASIC Standard Cell Customization under 45nm and 7nm Technology

Overview: Extend the standard cell library in very large scale integrated circuit (VLSI) designs for better VLSI circuit performance and lower power consumption under 45nm and 7nm technology.

Flow:

Extract new standard cells from digital circuits based on the Frequent Subgraph Mining (FSM) algorithm.
Synthesize the minimal transistor network for the extracted new standard cells by our proposed automatic synthesis tool, MiniTNtk (published at ICCAD'23), which can achieve the minimum transistor networks over benchmarks.
Automatically generate the VLSI layout for the extended standard cells and extract parasitic parameters.
Use the extended standard cell library to do logic synthesis over EPFL benchmarks, reducing area by at most 12.6%.